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教師小檔案
另開新視窗江正雄老師照片
江正雄
Jen-Shiun Chiang
  • 職稱: 教授

  • Ph.D.: 1992, 美國 德州農工大學 電機博士

  • 專長(Specialties):
    電腦運算、數位VLSI 設計、信號VLSI 設計、類比積體電路設計

  • 研究室: Room E684

  • 研究研究室: 前瞻性混合作業型系統(原VLSI)

  • 分機: +886-2-26215656 ext 3055. [886: Taiwan Country Code].

  • E-Mail: chiang@ee.tku.edu.tw

  • WebSite:
自我介紹
  • 經歷
    • 淡江大學電機系副教授(1992.8~ 2006.1)
    • 淡江大學電機系主任兼所長(2000.8~2006.8)
    • 淡江大學電機系教授(2006.1~ )

  • Jen-Shiun Chiang received the B.S. degree in electronics engineering from Tamkang University, Taipei, Taiwan, in 1983, the M.S. degree in electrical engineering from University of Idaho, Moscow Idaho, USA, in 1988, and the Ph.D. degree in the electrical engineering from Texas A&M University, College Station Texas, USA, in 1992. He joined the faculty member of the Department of Electrical Engineering at Tamkang University in 1992 as an associate professor. Currently he is a professor at the department. Dr. Chiang’s research interest includes digital signal processing for VLSI architecture, architecture for image data compressing, SOC design, analog to digital data conversion, and low power circuit design.
課程內容
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研究成果
  • 期刊論文(Reference paper)
    • Hsin-Liang Chen, Po-Sheng Chen, and Jen-Shiun Chiang, “A low-offset low-noise sigma-delta modulator with pseudorandom chopper-stabilization technique,” IEEE Transactions on Circuits and Systems, Accepted paper. (SCI, EI)

    • Chih-Hsien Hsia, Jing-Ming Guo, and Jen-Shiun Chiang, “An improved low complexity algorithm for 2-D integer lifting-based discrete wavelet transform using symmetric mask-based scheme,” IEEE Transactions on Circuits and Systems for Video Technology, Accepted paper. (SCI, EI)

    • Jen-Shiun Chiang, Han-Ting Lin, and Chih-Hsien Hsia, “Novel fast block motion estimation using diamond-arc-hexagon search patterns,” Journal of the Chinese Institute of Engineers, vol. 31, no. 6, pp. 955-966, September 2008. (SCI, EI)

    • Yang-Han Lee, Jen-Shiun Chiang, Yen-Hsih Chou, Yu-Shih Lee, “Low-Power/High-Speed Scalable and Subchannelizable FFT Architecture for SOFDMA Application,” Tamkang Journal of Science and Engineering: An International Journal, vol. 11, no. 3, pp. 313-324. (EI)

    • Fun Ye, Chih-Hao Kuei, and Jen-Shiun Chiang, “Radix-8 New Svobota-Tung Divider with Carry Free Characteristic for Precsaling,” Tamkang Journal of Science and Engineering: An International Journal, Accepted full paper. (EI)

    • Jen-Shiun Chiang, Chih-Hsien Hsia, and Tsai-Yuan Teng, “Fast intra prediction mode decision algorithm for 4×4 blocks in H.264/MPEG-4 AVC,” Tamkang Journal of Science and Engineering: An International Journal, , vol. 11, no. 1, pp. 49-54, March 2008. (EI)

    • Hsin-Chuan Chen and Jen-Shiun Chiang, “High-Performance Sequential MRU Cache Using Valid-Bit Assistant Search Algorithm,” Journal of Circuits, Systems, and Computers, vol. 16, no. 4, pp. 613-626, December 2007. (SCI)

    • Chih-Hsien Hsia, Jen-Shiun Chiang, and Sin-Guo Chou, “High efficiency and low complexity motion estimation algorithm for MPEG-4 AVC/H.264 coding,” Tamkang Journal of Science and Engineering: An International Journal, vol. 10, no. 3, pp. 221-234, October 2007. (EI)

    • Chih-Hsien Hsia and Jen-Shiun Chiang, “A memory-efficient VLSI architecture for 2-D integer lifting-based discrete wavelet transform,” WSEAS Transactions on Circuits and Systems, vol. 6, issue 3, pp. 355-363, March 2007. (EI)

    • Jen-Shiun Chiang, Chun-Hau Chang, Chang-You Hsieh, and Chih-Hsien Hsia, “High efficient EBCOT with parallel-coding architecture for JPEG2000,” EURASIP Journal on Applied Signal Processing, vol. 2006, article ID 42568, pp. 1-14, 2006. (SCI, EI)

    • Chih-Hsien Hsia, Wei-Ming Li, Tsung-Ta Lin, Ting-Wei Huang and Jen-Shiun Chiang, “A Memory-Efficient VLSI Architecture for Two-Dimensional Inverse Discrete Wavelet Transform,” Journal of Jin-Wen Institute of Technology, vol. 16, no. 2, pp. 49-78, June 2006.

    • Jen-Shiun Chiang and Hsin-Liang Chen, "Opamp gain insensitive MASH sigma delta modulator for wide bandwidth applications," Kluwer Journal of Analog Integrated Circuits and Signal Processing, vol.47, no.3, pp.281-291, June 2006. (SCI, EI)

    • Hsin-Chuan Chen and Jen-Shiun Chiang, “A low-jitter phase-interpolation direct digital synthesizer using single capacitor integration,” International Journal of Electrical Engineering, vol. 12, no. 3, pp.225-232, August 2005. (EI)

    • Hsin-Chuan Chen and Jen-Shiun Chiang, “Design of an adjustable-way cache for energy reduction,” Journal of the Chinese Institute of Engineers, vol. 28, no. 4, pp. 691- 700, July 2005. (SCI)

    • Jen-Shiun Chiang, Teng-Hung Chang, and Pao-Chu Chou, “Low distortion and swing suppression sigma-delta modulator with extended dynamic range scheme,” Kluwer Journal of Analog Integrated Circuits and Systems, vol.45, no.2, pp.169-182, November 2005. (SCI, EI)

    • Jen-Shiun Chiang, Cheng-Chih Chien, Jian-Kao Chen and Hsin-Guo Chou, “An Efficient VLSI Architecture Public-key Cryptosystem,” Tamkang Journal of Science and Engineering: An International Journal, vol. 7, No.4, pp. 241-250, September 2004. (EI)

    • Fun Ye, Jen-Shiun Chiang, Chun-Wen Chen, and Yu-Chen Sung, “Dynamic bias circuits for efficiency improvement of RF power amplifier,” Tamkang Journal of Science and Engineering: An International Journal, vol. 7, no. 3, pp. 183-188, September 2004. (EI)

    • Hsin-Chuan Chen and Jen-Shiun Chiang, “A low-jitter phase-interpolation DDS using dual-slope integration,” IEICE Electronics Express, vol. 1, no. 12, pp. 333-338, September 2004. (SCI, EI)

    • Jen-Shiun Chiang, Pao-Chu Chou, and Teng-Hung Chang, “Dual-band sigma-delta modulator for wideband receiver applications”, IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, vol. E87-A, no. 2, pp. 311-323, February 2004. (SCI, EI)

    • Hsin-Chuan Chen and Jen-Shiun Chiang, “Design of a low-lower configurable-way cache applied in multiprocessor systems,” IEICE Transactions on Information and Systems, vol.E86-D, no.9 pp.1542-1548, September 2003. (SCI, EI)

    • Jen-Shiun Chiang, Pao-Chu Chou, and Teng-Hung Chang, “A wideband cascaded sigma-delta modulator with improved non-linearity effects,” International Journal of Electronics. vol. 90, no. 4, pp. 255-275, August 2003. (SCI, EI)

    • Jen-Shiun Chiang and Min-Show Tsai, “A radix-4 new svota-tung divider with constant timing complexity for precsaling,” Kluwer Journal of VLSI Signal Processing, vol. 33, no. 1/2, pp. 117-124, January/ February 2003. (SCI, EI)

    • Jen-Shiun Chiang, Teng-Hung Chang and Pou-Chu Chou, “Cascaded feedforward sigma-delta modulator for wide bandwidth applications,” Tamkang Journal of Science and Engineering: An International Journal, vol. 4, no. 3, pp. 155-164, September 2001. (EI)

    • Jen-Shiun Chiang, Hsin-Chuan Chen, and Yu-Sen Lin, “High speed sequential MRU caches,” Communications of Institute of Information and computing Machinery, vol. 4, no. 4, pp. 1-15, December 2001.

    • Jen-Shiun Chiang, Hung-Da Chung, and Min-Show Tsai, “Carry-free radix-2 subtractive division algorithm and implementation of the divider,” Tamkang Journal of Science and Engineering: An International Journal, vol. 3, no. 4, pp. 249-255, December 2000. (EI)

    • Jen-Shiun Chiang, Eugene Lai, and Jun-Yao Liao, “A radix-2 non-restoring 32-b/32-b ring divider with asynchronous control scheme,” Tamkang Journal of Science and Engineering: An International Journal, vol. 2, no. 1, pp. 37-44, June 1999. (EI)

    • Jen-Shiun Chiang and Kuang-Yuan Chen, “The design of an all digital phase locked loop with small DCO hardware and fast phase lock,” IEEE Transaction on Circuits and Systems Part II, vol. 46, no. 7, pp. 945-950, July 1999. (SCI, EI)

    • Jen-Shiun Chiang and Jun-Yao Liao, “The design and implementation of a pipelined multiplier associated with a new pass transistor asynchronous control unit,” Proceedings of the National Science Council, vol. 23, no. 6, pp. 744-750, 1999. (SCI, EI)

    • Jen-Shiun Chiang and Hsiang-Chou Huang, “Novel architecture for two dimensional high throughput rate real time discrete cosine transform and the VLSI Design,” International Journal of Electronics, vol. 83, no. 4, pp. 519- 527, August 1997. (SCI, EI)

    • 江正雄和張世昌, “The design of a 16-b x 16-b residue number system multiplier,” 淡江學報, pp. 127- 140, 1995.

    • Mi Lu and Jen-Shiun Chiang, “A novel division algorithm for the residue number system,” IEEE Transaction on Computers, vol. 41, no. 8, pp. 1026-1032, August 1992. (SCI, EI)


  • [研討會論文(Conference papers)]
    • Chih-Hsien Hsia, Ding-Wei Huang, Jen-Shiun Chiang, and Zong-Jheng Wu, “Moving objects tracking using symmetric mask-based scheme,” IEEE International Conference on Information Assurance and Security, Accepted paper, August 2009. (EI)

    • H.-L. Chen and Jen-Shiun Chiang, IEEE International Symposium on Circuits and Systems, Accepted paper, May 2009. (EI)

    • Chih-Hsien Hsia, Jing-Ming Guo, Jen-Shiun Chiang, and Chia-Hui Lin, IEEE International Symposium on Circuits and Systems, Accepted paper, May 2009. (EI)

    • Jen-Shiun Chiang, Ting-Hao Hwang, and Tsung-Ta Lin, “High Efficiency Architecture of Escot with Word-Level Pass Concurrent Context Modeling Scheme for SVC,” IEEE International Symposium on Circuits and Systems, Accepted paper, May 2009. (EI)

    • Wei-Ming Li, Chih-Hsien Hsia, and Jen-Shiun Chiang, IEEE International Symposium on Circuits and Systems, Accepted paper, May 2009. (EI)

    • Kun-Sheng Chen, Jen-Shiun Chiang, and Chih-Hsien Hsia, “A motion estimation method of predicting SAD based on sub-macro-block fixed-sample-points SSAD,” Workshop on Consumer Electronics, Accepted paper, December 2008.

    • Shih-Hung Chang, Chih-Hsien Hsia, Wei-Husan Chang, and Jen-Shiun Chiang, “A feature-based visual self-localization algorithm for humanoid soccer robot system,” CACS International Automatic Control Conference, Accepted paper, November 2008.

    • Chih-Hsien Hsia and Jen-Shiun Chiang, “New memory-efficient hardware architecture of 2-D dual-mode lifting-Based discrete wavelet transform for JPEG2000,” IEEE International Conference on Communication Systems, Accepted paper, November 2008. (EI)

    • Chih-Hsien Hsia and Jen-Shiun Chiang, “A high-performance and memory-efficient parallel architecture for the 5/3 and 9/7 DWT of JPEG2000 encoder,” IPPR Conference on Computer Vision, Graphics, and Image Processing, Session A-1, no.2, August 2008.

    • Jen-Shiun Chiang, Chih-Yueh Chang, Chih-Hsien Hsia, and Wei-Husan Chang, “A new video object segmentation algorithm using the morphological technique,” IEEE International Conference on Ubi-media Computing, pp. 255-260, July 2008. (EI)

    • Jen-Shiun Chiang, Tsung-Ta Lin, and Ting-Hao Hwang, “Low cost architecture for JPEG2000 encoder without code-block memory,” IEEE International Conference on Multimedia & Expo, pp. 137-140, June 2008. (EI)

    • Jen-Shiun Chiang, Ting-Hao Hwang, Tsung-Ta Lin, and Chih-Hsien Hsia, “High efficiency architecture of ESCOT with pass concurrent context modeling scheme for scalable video coding,” IEEE International Symposium on Circuits and Systems, pp. 2801-2804, May 2008. (EI)

    • 夏至賢, 陳延任, 江正雄, “應用於H264/AVC之高效能去方塊濾波器硬體架構設計,” 全國電子設計創意競賽論文集, 第52-57頁, 民國97年4月.

    • Chih-Hsien Hsia, Jing-Ming Guo, and Jen-Shiun Chiang, “A new fast algorithm for 2-D integer discrete wavelet transform using symmetric mask-based scheme,” IEEE International Symposium on Multimedia, pp. 57-64, December 2007. (EI)

    • Chih-Hsien Hsia, Jen-Shiun Chiang, Ying-Hong Wang, and Tsai-Yuan Teng, “Fast intra prediction mode decision algorithm for H.264/AVC video coding standard,” IEEE International Conference on Intelligent Information Hiding and Multimedia Signal Processing, vol. 2, pp. 535-538, November 2007. (EI)

    • Hsin-Liang Chen, Yi-Sheng Lee, and Jen-Shiun Chiang, “Low power sigma delta modulator with dynamic biasing for audio applications,” VLSI Design/CAD Symposium, P3A-9, August 2007.

    • Jen-Shiun Chiang, Hsin-Liang Chen, Yao-Tsung Chang and Meng-Hsuan Ho, “80-S/s delta sigma modulators for IR thermometer,” VLSI Design/CAD Symposium, C2-6, August 2007.

    • Hsin-Liang Chen, Ming-Chi Tsai, and Jen-Shiun Chiang, “A Low Power Wide Bandwidth Second Order Continuous Time Sigma Delta Modulator with Single Amplifier Scheme”, IASTED International Conference on Circuits, Signals, and Systems, July 2007.(EI)

    • Chih-Yueh Chang, Jen-Shiun Chiang, Fun Ye, and Chih-Hsien Hsia, “An efficient video object segmentation based on mask pre-filling algorithm,” Conference on Communication Applications, pp. 109-112, March 2007.

    • Chih-Hsien Hsia, Jen-Shiun Chiang, and Yen-Jen Chen, “An efficient VLSI architecture to accelerate the deblocking filter for H264/AVC,” Conference on Communication Applications, pp. 147-152, March 2007.

    • Chih-Hsien Hsia, Jing-Ming Guo, and Jen-Shiun Chiang, “Complexity reduction for 2-D integer lifting-based DWT using symmetric mask scheme,” IPPR Computer Vision, Graphics, and Image Processing Conference, pp. 1040-1047, August 2006.

    • Han-Ting Lin and Jen-Shiun Chiang, “A Diamond-Arc-Hexagon Search Algorithm for Fast Block Motion Estimation,” IEEE International Symposium on Signal Processing and Information Technology, Accepted. (EI)

    • Han-Ting Lin and Jen-Shiun Chiang, “Hierarchical Predictable Hexagon Search Algorithm for H.264 Coding,” IEEE International NEWCAS Conference, Accepted. (EI)

    • Yih G. Jan, Ming-Chi Tsai, Hsin-Liang Chen, Jen-Shiun Chiang, and Yao-Tsung Chang,” A Low Power Wide Bandwidth Second-Order Continuous-Time Delta-Sigma Modulator with Single Amplifier Scheme,” VLSI Design/CAD Symposium, August 2006.

    • Han-Ting Lin and Jen-Shiun Chiang, “ Hybrid Predictable Hexagon with Three-Step Search Algorithm for Block Motion Estimation, ” 微電子技術發展與應用研討會,2006年5月.

    • 李偉銘、夏至賢、戴嘉宏與江正雄, “即時有效率之二維離散小波反轉換VLSI架構,” 微電子技術發展與應用研討會, 2006年5月.

    • Jen-Shiun Chiang, Yi-Tsung Li, Hsin-Liang Chen, and Ming-Chi Tsai, “A 20-MS/s sigma delta modulator for 802.11a applications”, IEEE International Symposium on Circuits and Systems, pp. 1888-1891, May 2006. (EI)

    • Jen-Shiun Chiang, Chang-Yo Hsieh, Jin-Chan Liu, and Cheng-Chih Chien, “Concurrent bit-plane coding architecture for EBCOT in JPEG2000,” IEEE International Symposium on Circuits and Systems, pp. 4595-4598, May 2006. (EI)

    • 夏至賢、李偉銘、黃丁威、林宗達與江正雄, “新式快速演算法適用於二維離散小波轉換,” 資訊管理暨實務研討會, 頁1090-1102, 2005年12月.

    • Jen-Shiun Chiang, Chih-Hsien Hsia, Tsung-Ta Lin, Wei-Ming Li and Ting-Wei Huang, “A new mask-based algorithm for 2-D discrete wavelet transform processor, “ National Computer Symposium, December 2005.

    • 翁慶昌, 李揚漢, 謝景棠, 江正雄, 饒建奇, 郭建宏, 葉豐輝, 周永山, 曾憲威, 王榆淙 “智慧型無線光導盲杖導引系統暨導盲機器人之設計,” National Workshop on Internet and Communication Technology, pp. 89-94, November 16, 2005.

    • 江正雄與李後璋, ”高傳輸率維特比解碼器”, 民生電子暨信號處理研討會, 2005年11月.

    • Chih-Hsien Hsia, Jen-Shiun Chiang, Ting-Wei Huang, Wei-Ming Li and Tsung-Ta Lin, ” Design of high-efficiency multimedia signal processing IP for 2-D DWT VLSI architecture,” Workshop on Consumer Electronics and Signal Processing, November 2005.

    • Jen-Shiun Chiang, Yi-Tsung Li, Hsin-Liang Chen, and Ming-Chi Tsai, “A 20-MS/S sigma delta modulator for 802.11a applications”, VLSI Design/CAD Symposium, August 2005.

    • Jen-Shiun Chiang, Ming-Hung Du, Hsin-Liang Chen, and Yu-Chen Sung, “A138.24-MHz continuous-time band-pass sigma delta modulator for digital IF application,“ International Technical Conference On Circuits/System, Computers and Communications, July 2005.

    • Jen-Shiun Chiang, Chun-Cheng Wu, Hsin-Liang Chen, and Yi-Tsung Li, “Low power sigma-delta modulator with dynamic biasing for voice band applications,“ International Technical Conference On Circuits/System, Computers and Communications, July 2005.

    • Fun Ye, Jen-Shiun Chiang, Yi- Tsung Lee, Pou-Chu Chou and Hsin-Jung Chen, “A low power sigma delta modulator for GSM and W-CDMA applications,” IEE International Conference on Advanced A/D and D/A Conversion Techniques and Their Applications, pp. 309-312, July 2005.

    • Jen-Shiun Chiang, and Chih-Hsien Hsia, “An efficient VLSI architecture for 2-D DWT using lifting scheme,” IEEE International Conference on Systems and Signals, pp. 528- 531, April 2005.

    • Jen-Shiun Chiang, Chih-Hsien Hsia, Hsin-Jung Chen, and Te-Jung Lo, “VLSI architecture of low memory and high speed 2-D lifting-based discrete wavelet transform for JPEG2000 applications , ” IEEE International Symposium on Circuits and Systems Conference, pp. 4554- 4557, May 2005. (EI)

    • Jen-Shiun Chiang, Sin-Guo Jhou, Yen-Jen Chen, and Je-Yu Tzou, “Image quality evaluation based on separating block PSNR for digital video coding,” International Conference on Imaging Science, Systems, and Technology: Computer Graphics, June 27-30, 2005.

    • Jen-Shiun Chiang, Chih-Hsien Hsia, and Hsin-Jung Chen, “2-D discrete wavelet transform with efficient parallel scheme,” International Conference on Imaging Science, Systems, and Technology: Computer Graphics, pp. 193- 197, June 2005.

    • Jen-Shiun Chiang, Hsin-Guo Chou, and Je-Yu Tzou "An efficient and regular motion estimation algorithm for MPEG4-AVC/H.264 coding," IEEE International Workshop on Cellular Neural Networks and their Applications, pp. 253-256, May 2005. (EI)

    • Hsin-Chuan Chen; Jen-Shiun Chiang, “Low-power way-predicting cache using valid-bit pre-decision for parallel architectures,” IEEE International Conference on Advanced Information Networking and Applications, vol. 2, pp. 203-206, March 2005. (EI)

    • Jen- Shiun Chiang, Chih-Hsien Hsia, Te-Jung Lo, and Hsin-Jung Chen, “ Highly efficient VLSI architecture for 2-D discrete wavelet transform, ” National Symposium on Telecommunications conference, DSP-2-3, pp. 891- 895, December 2004.

    • Jen-Shiun Chiang, Ron-Yi Liu, Ming-Hung Tu and Yu-Cheng Sung,“An IF 138.24MHz continuous-time band-pass sigma delta modulator for digital IF application”, VLSI Design/CAD Symposium, August 2004.

    • Jen-Shiun Chiang and Chun-Cheng Wu, “Low power sigma-delta modulator with dynamic biasing for speech Codecs”, VLSI Design/CAD Symposium, August 2004.

    • Jen-Shiun Chiang, Hsin-Liang Chen, Pou-Chu Chou, “A 2.5-V, 14-bit MASH sigma-delta modulator for ADSL”, IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 24-27, Aug 2004. (EI)

    • Jen-Shiun Chiang, Chun-Hau Chang, Yu-Sen Lin, and Chang-You Hsieh, Chih-Hsien Hsia, “High-speed EBCOT with dual content-modeling coding architecture for JPEG2000”, IEEE International Symposium on Circuits and Systems, vol. 3, pp. 23-26, May 2004. (EI)

    • Jen-Shiun Chiang, Chun-Hau Chang, Yu-Sen Lin, and Chang-You Hsieh, “High throughput rate EBCOT architecture for JPEG2000,” IEEE Midwest Symposium on Circuits and Systems, vol. 2, pp.610 – 613, December 2003. (EI)

    • Rainfield Yen, Yang-Han Lee, Jen-Shiun Chiang, Liang-Lin Jau, Wei-Chung Cheng, and Wei Chien “Co-design simulation (hardware tools, software tools, and channel modeling) for IEEE 802.11a,” Workshop on Consumer Electronic, November 27-28, 2003.

    • Yang-Han Lee, Liang-Lin Jau, Jen-Shiun Chiang, Sheng-Kai Yu, Ming-Hsueh Chuang and Wei Chien “Optimal wordlength of pipelined FFT/IFFT design for IEEE 802.11g System,” Workshop on Consumer Electronic, November 2003.

    • Yang-Han Lee, Liang-Lin Jau, Jen-Shiun Chiang, Ming-Hsueh Chuang, Sheng-Kai Yu and Wei Chien “, A partitioned minimum metric selection method for high speed viterbi decoder” Workshop on Consumer Electronic, November 2003.

    • 江正雄、林國藩與李鴻欽,”具能量回收之改良式零電流切換功因校正器之設計,”臺灣電力電子研討會,頁1-5,2003年.

    • Jen-Shiun Chiang, Jim-Wen Chen, “2.4GHz CMOS power amplifier with dynamic bias circuits for efficiency improvement,” VLSI Design/CAD Symposium, pp. 125-128, August 2003.

    • Hsin-Chuan Chen, Jen-Shiun Chiang, and Hsing-Ying Chen, “A jitter-free phase-interpolation direct digital synthesizer using two-phase integration,” VLSI Design/CAD Symposium, pp. 565-565, August 2003.

    • Jen-Shiun Chiang, and Hsin-Liang Chen, “A MASH sigma-delta modulator with low-distortion architecture,” International Conference on Embedded Systems and Applications, June 2003.

    • Timothy.K. Shih, Louis H. Lin and Jen-Shiun Chiang, “Progressive image transmission by adaptive interpolation,” IEEE International Conference on Multimedia and Expo, vol. 2, pp. 141-4, July 2003. (EI)

    • Jen-Shiun Chiang, Pao-Chu Chou, and Teng-Hung Chang, “Dual-mode sigma-delta modulator for wideband receiver applications,” IEEE International Symposium on Circuits and System, vol. 1, pp. 25-28, May 2003. (EI)

    • Jen-Shiun Chiang, Ying-Hong Wang, Chih-Hsiao Tsai and Chih-Peng Hsu, ”Location management and multimedia communication service based on Mobile IP and cellular IP network,” IEEE International Conference on Advanced Information Networking and Applications, pp. 223 – 226, March 2003. (EI)

    • Jen-Shiun Chiang, Hsueh-Ping Chen and Cheng-Ming Ying, “A 1V 0.54 /sp lmu/W fourth order switched capacitor filter with switched op amp technique for cardiac pacemaker sensing channel”, IEEE International Symposium on Circuits and System, vol. 1, pp. 481-484, May 2003. (EI)

    • Hsin-Chuan Chen, Jen-Shiun Chiang, and Chung-Yu Kuo “A ROM-less direct digital synthesizer using piecewise linear approximation”, VLSI Design/CAD Symposium, pp. 496-499, August 2002.

    • Jen-Shiun Chiang, Teng-Hung Chang, and Pao-Chu Chou, “A low-distortion and swing suppression sigma-delta modulator with extended dynamic range”, IEEE Asia-Pacific Conference on ASIC, pp. 9-12, August 2002. (EI)

    • Jen-Shiun Chiang, Teng-Hung Chang, and Chia-Pao Chang “Novel multi-Stage wide bandwidth sigma-delta modulator with swing suppression,” WSEAS International Multiconference on Circuits, Systems, Communications and Computers, pp. 7331-7334, July 2002.

    • Jen-Shiun Chiang, Teng-Hung Chang, “Novel wideband cascaded sigma-delta modulator with digital on-line calibration,” WSEAS International Multiconference on Circuits, Systems, Communications and Computers, pp. 7121-7124, July 2002.

    • Jen-Shiun Chiang, Hsueh-Ping Chen “1V sample-and-hold circuit using switched op amp,” WSEAS International Multiconference on Circuits, Systems, Communications and Computers, pp. 7031-7033, July 2002.

    • Jen-Shiun Chiang, Pao-Chu Chou, and Hsin-Lian Chen “Dual quantization ΣΔ modulator with noise shaping improved,” WSEAS International Multiconference on Circuits, Systems, Communications and Computers, pp. 7021-7024, July 2002.

    • Jen-Shiun Chiang, Teng-Hung Chang, and Pao-Chu Chou, “A novel wideband low-distortion cascaded sigma-delta ADC”, IEEE International Symposium on Circuits and System, vol. 1, pp. 636-639, May 2002. (EI)

    • Jen-Shiun Chiang, Yu-Sen Lin, and Chang-Yo Hsieh “Efficient pass-parallel architecture for EBCOT in JPEG2000”, IEEE International Symposium on Circuits and System, vol. 1, pp. 773-776, May 2002. (EI)

    • Hsin-Chuan Chen, Jen-Shiun Chiang and Yu-Sen Lin, "A fast sequential MRU cache with competitive hardware cost", International Conference on Parallel and Distributed Computing, Application and Technologies, pp. 220-227, Jul. 2001.

    • Hsin-Chuan Chen and Jen-Shiun Chiang, “Design of an adjustable-way set-associative cache,” IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, vol. 1, pp.315-318, August 2001. (EI)

    • Jen-Shiun Chiang, Pou-Chu Chou, and Teng-Hung Chang, “Novel noise shaping high-order sigma-delta modulator for wide bandwidth applications,” International Symposium on Integrated Circuits, Devices & Systems, pp. 67-70, 2001.

    • Jen-Shiun Chiang, Yi-Fang Chiu, and Teng-Hung Chang, “An overlapped row column high throughput two-dimensional DCT/IDCT architecture for real-time image and video system,” IEEE International Conference on Electronics, Circuits, and Systems, pp. 867-870, September 2001. (EI)

    • Jen-Shiun Chiang, Teng-Hung Chang, and Pou-Chu Chou, “Novel noise shaping of cascaded sigma-delta modulator for wide bandwidth applications,” IEEE International Conference on Electronics, Circuits, and Systems, vol.3, pp. 1379-1382, September 2001. (EI)

    • Jen-Shiun Chiang, Pou-Chu Chou, and Teng-Hung Chang, “Cascaded feedforward sigma-delta modulator for wide bandwidth applications,” IEEE International Conference on Electronics, Circuits, and Systems, vol.2, pp. 1039-1042, September 2001. (EI)

    • Jen-Shiun Chiang, Min-Shiou Tsai and Yi-Fang Chiu, “A high speed radix-4 carry free division architecture”, VLSI Design/CAD Symposium, pp. 175-178, August 2000.

    • Jen-Shiun Chiang and Min-Da Chiang, “The design of a 1.5V, 10-Bit, 10 Msamples/s low power pipelined analog-to-digital converter”, IEEE International Symposium on Circuits and System, vol. 1, pp. 443-446, May 2000. (EI)

    • Jen-Shiun Chiang, Hung-Da Chung, and Min-Hsiu Tsai , “A Radix-2 general division algorithm with carry-free scheme and the divider implementation”, IEEE International Conference on Electronics, Circuits and Systems, vol.1, pp. 569-572, September 1999. (EI)

    • Jen-Shiun Chiang and Jian-Kao Chen, “An efficient VLSI architecture for RSA public-key cryptosystem”, IEEE International Symposium on Circuits and System, vol. 1, pp. 496-499, May 1999. (EI)

    • Jen-Shiun Chiang and Hung-Da Chung, “A carry-free radix-2 general division algorithm and the application to the design of a 32-b/32-b divider”, VLSI Design/CAD Symposium, pp. 234-237, August 1998.

    • Jen-Shiun Chiang and Ming-Da Chiang, “A 2-dimensional DCT/IDCT with overlapped row-column operation”, IEEE International Workshop on Intelligent Signal Processing and Communication Systems, vol. 2, pp. 580-583, November 1998. (EI)

    • Jen-Shiun Chiang and Pao-Chu Chou, “A 3.3V two stage fourth-order sigma-delta modulator with gain compensation technique”, IEEE Asia Pacific Conference on Circuits and System, pp. 1-4, November 1998. (EI)

    • Jen-Shiun Chiang, Jau-Liang Chen, and Eugene Lai, “A 3.3V delta-sigma A/D converter with area-efficient and low-power digital filter for decimation on speech coding”, International Workshop on Design of Mixed-Mode Integrated Circuits and Application, pp. 123-126, 1998.

    • Jen-Shiun Chiang and Kuang-Yuan Chen, “A 3.3V all digital phase-locked loop with small DCO hardware and fast phase lock”, IEEE International Symposium on Circuits and System, vol. 3, pp. 554-557, May 1998. (EI)

    • Jen-Shiun Chiang and Jun-Yao Liao, “The design and implementation of an asynchronous radix-2 non-restoring 32-b/32-b ring divider”, IEEE International Symposium on Circuits and System, vol. 2, pp. 173-176, May 1998. (EI)

    • Kuang-Yuan Chen and Jen-Shiun Chiang, “The design and implementation of a 3.3V 400MHz all digital phase-locked loop,” VLSI Design/ CAD Symposium, August 1997. Jen-Shiun Chiang and Jun-Yao Liao, “A novel asynchronous control unit and the application to a pipelined multiplier”, IEEE International Symposium on Circuits and System, vol. 2, pp. 169-172, May 1998. (EI)

    • Jen-Shiun Chiang and Chi-Wei Hu, “The design of a delta-sigma modulator with low clock feed through boise, op-amp gain compensation, and more correctly transferring charges between capacitors,” IEEE International Symposium on Circuits and System, vol. 3, pp. 2016-2019, May 1997. (EI)

    • Jen-Shiun Chiang and Hsiang-Chou Huang, “New architecture for high throughput-rate real-time 2-D DCT and the VLSI design,” IEEE International ASIC Conference and Exhibit, pp. 219-222, September 1996. (EI)


  • 委託研究案
    • 98 具有教育及競賽功能的人型機器人系統之設計與開發- 機器人可適應性視覺即時處理之低功率系統晶片設計(3/3)

    • 97 具有教育及競賽功能的人型機器人系統之設計與開發- 機器人可適應性視覺即時處理之低功率系統晶片設計(2/3)

    • 96 具有教育及競賽功能的人型機器人系統之設計與開發- 機器人可適應性視覺即時處理之低功率系統晶片設計(1/3) 國科會 NSC-96-2218-E-032-003

    • 96 次世代異質性通信系統的低功率、高速度積分三角式類比數位轉換器研製(I) 國科會NSC-96-2221-E-032-053

    • 95 無線光通訊之智慧型盲人預警監控及導引網路系統-子計畫一:提昇私校研發能量專案計畫-無線光傳收機之研製(3/3) 國科會NSC-93-2475-E-032-002-URD

    • 94 無線光通訊之智慧型盲人預警監控及導引網路系統-子計畫一:提昇私校研發能量專案計畫-無線光傳收機之研製(2/3) 國科會NSC-93-2475-E-032-002-URD

    • 93 無線光通訊之智慧型盲人預警監控及導引網路系統-子計畫一:提昇私校研發能量專案計畫-無線光傳收機之研製(1/3) 國科會NSC-93-2475-E-032-002-URD

    • 93 應用於IEEE 802.11a系統之低功率高效能類比數位與數位類比轉換器(I) 國科會NSC-93-2215-E-032-001

    • 92 應用於第三代行動通訊接收端之寬頻及低功率類比數位轉換器之研究與發展 國科會NSC-92-2218-E-032-007-

    • 91 使用在行動通訊上具寬頻及多重通訊協定之類比/數位轉換器新架構之研究及其晶片實現 國科會NSC-91-2215-E-032-003

    • 90 IC晶片之量測與相關應用之研究 富晶半導體公司

    • 90 無線寬頻接收端之寬頻類比/數位轉換器與可調適性濾波池之新架構研究與設計 國科會NSC-90-2215-E-032-001

    • 89 IC晶片之量測與相關應用之研究 富晶半導體公司

    • 89 多位元與高精準度快速除法器之演算法則與硬體架構之研究與發展 國科會NSC-89-2215-E-032-005

    • 88 3V_100MHZ正反離散餘弦轉換器IP模組之研究與晶片研製 國科會NSC-88-2215-E-032-003

    • 87 無進位式高速除法器之演算法則與硬體架構之研究與發展 國科會NSC-88-2215-E-032-001

    • 86 非同步電路控制單元研究與其相關電路元件和系統之設計發展 國科會NSC-87-2215-E-032-004

    • 83 應用餘數定理之除法器 國科會NSC-84-0404-E-032-003

    • 82 應用餘數定理之除法器 國科會 NSC-83-0404-E-032-003

    • 82 積體電路細胞元資料庫之開發與相關之應用研究 國科會 NSC-83-0404-E-032-001

    • 81 應用餘數系統之快速16位元x16位元乘法器 國科會 NSC-82-0404-E-032-044


  • Hsin-Liang Chen, Po-Sheng Chen, and Jen-Shiun Chiang, “A low-offset low-noise sigma-delta modulator with pseudorandom chopper-stabilization technique,” IEEE Transactions on Circuits and Systems, Accepted paper. (SCI, EI)

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